Since the development of the integrated circuit (IC), the semiconductor industry has sought to continue to improve the performance or size of the IC. Many of these improvements have focused on smaller feature sizes so that the speed of the IC can be increased. By decreasing the feature sizes, the density of devices (e.g., transistors, diodes, resistors, capacitors, etc.) on the IC has increased. By increasing the density, distances between devices generally decreases, which allows for a smaller resistance and capacitance between devices. Thus, a resistance-capacitance (RC) time constant can be decreased.
By decreasing features sizes and increasing density, material and processing challenges have generally occurred. In some instances, by increasing the density, volumes in which certain materials are to be deposited have decreased in size. This decrease in size may cause conventional processing and deposition techniques to not render acceptable structures. For example, the material deposited to fill the decreased volume may not actually fill the volume. Hence, voids in these volumes may occur.
If voids occur in a semiconductor structure, the structure may be defective. For example, with a void, leakage issues may occur rendering the structure unusable. Thus, for shrinking features size technologies, the yield of the structures can be negatively affected by using conventional processing and deposition techniques.